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low distortion differential adc driver ad8138 rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features easy to use, single-ended-to-differential conversion adjustable output common-mode voltage externally adjustable gain low harmonic distortion ?94 dbc sfdr @ 5 mhz ?85 dbc sfdr @ 20 mhz ?3 db bandwidth of 320 mhz, g = +1 fast settling to 0.01% of 16 ns slew rate 1150 v/s fast overdrive recovery of 4 ns low input voltage noise of 5 nv/hz 1 mv typical offset voltage wide supply range +3 v to 5 v low power 90 mw on 5 v 0.1 db gain flatness to 40 mhz available in 8-lead soic and msop packages applications adc drivers single-ended-to-differential converters if and baseband gain blocks differential buffers line drivers pin configuration ?in 1 v ocm 2 v+ 3 +out 4 +in 8 nc 7 v? 6 ?out 5 nc = no connect ad8138 01073-001 figure 1. typical application circuit ain ain avss 499? 499? 499? 499? 5 v 5v ad8138 + ? digital outputs v ocm v in adc v ref avdd dvdd 01073-002 figure 2. general description the ad8138 is a major advancement over op amps for differential signal processing. the ad8138 can be used as a single-ended-to-differential amplifier or as a differential-to- differential amplifier. the ad8138 is as easy to use as an op amp and greatly simplifies differential signal amplification and driving. manufactured on adis proprietary xfcb bipolar process, the ad8138 has a ?3 db bandwidth of 320 mhz and delivers a differential signal with the lowest harmonic distortion available in a differential amplifier. the ad8138 has a unique internal feedback feature that provides balanced output gain and phase matching, suppressing even order harmonics. the internal feed-back circuit also minimizes any gain error that would be associated with the mismatches in the external gain setting resistors. the ad8138s differential output helps balance the input to differential adcs, maximizing the performance of the adc. the ad8138 eliminates the need for a transformer with high performance adcs, preserving the low frequency and dc infor- mation. the common-mode level of the differential output is adjustable by a voltage on the v ocm pin, easily level-shifting the input signals for driving single-supply adcs. fast overload recovery preserves sampling accuracy. the ad8138 distortion performance makes it an ideal adc driver for communication systems, with distortion performance good enough to drive state-of-the-art 10-bit to 16-bit converters at high frequencies. the ad8138s high bandwidth and ip3 also make it appropriate for use as a gain block in if and baseband signal chains. the ad8138 offset and dynamic performance makes it well suited for a wide variety of signal processing and data acquisition applications. the ad8138 is available in both soic and msop packages for operation over ?40c to +85c temperatures.
ad8138 rev. f | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 pin configuration............................................................................. 1 typical application circuit ............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 d in to out specifications...................................................... 3 v ocm to out specifications ..................................................... 4 d in to out specifications...................................................... 5 v ocm to out specifications ..................................................... 6 absolute maximum ratings............................................................ 7 thermal resistance ...................................................................... 7 esd caution.................................................................................. 7 pin configuration and function descriptions............................. 8 typical performance characteristics ............................................. 9 test circuits..................................................................................... 15 operational description................................................................ 16 definition of terms.................................................................... 16 theory of operation ...................................................................... 17 analyzing an application circuit ............................................ 17 setting the closed-loop gain .................................................. 17 estimating the output noise voltage ...................................... 17 the impact of mismatches in the feedback networks ......... 18 calculating an application circuits input impedance......... 18 input common-mode voltage range in single-supply applications ................................................................................ 18 setting the output common-mode voltage .......................... 18 driving a capacitive load......................................................... 18 layout, grounding, and bypassing.............................................. 19 balanced transformer driver ....................................................... 20 high performance adc driving ................................................. 21 3 v operation ................................................................................. 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 1/06rev. e to rev. f changes to features.......................................................................... 1 added thermal resistance section and maximum power dissipation section........................................................................... 7 changes to balanced transformer driver section..................... 20 changes to ordering guide .......................................................... 23 3/03rev. d to rev. e changes to specifications ................................................................ 2 changes to ordering guide ............................................................ 4 changes to tpc 16........................................................................... 6 changes to table i ............................................................................ 9 added new paragraph after table i ............................................. 10 updated outline dimensions ....................................................... 14 7/02rev. c to rev. d addition of tpc 35 and tpc 36 .....................................................8 6/01rev. b to rev. c edits to specifications ......................................................................2 edits to ordering guide ...................................................................4 12/00rev. a to rev. b 9/99rev. 0 to rev. a 3/99rev. 0: initial version
ad8138 rev. f | page 3 of 24 specifications d in to out specifications at 25c, v s = 5 v, v ocm = 0, g = +1, r l, dm = 500 , unless otherwise noted. refer to figure 39 for test setup and label descriptions. all specifications refer to single-ended input and differential outputs, unless otherwise noted. table 1. parameter conditions min typ max unit dynamic performance ?3 db small signal bandwidth v out = 0.5 v p-p, c f = 0 pf 290 320 mhz v out = 0.5 v p-p, c f = 1 pf 225 mhz bandwidth for 0.1 db flatness v out = 0.5 v p-p, c f = 0 pf 30 mhz large signal bandwidth v out = 2 v p-p, c f = 0 pf 265 mhz slew rate v out = 2 v p-p, c f = 0 pf 1150 v/s settling time 0.01%, v out = 2 v p-p, c f = 1 pf 16 ns overdrive recovery time v in = 5 v to 0 v step, g = +2 4 ns noise/harmonic performance 1 second harmonic v out = 2 v p-p, 5 mhz, r l, dm = 800 ?94 dbc v out = 2 v p-p, 20 mhz, r l, dm = 800 ?87 dbc v out = 2 v p-p, 70 mhz, r l, dm = 800 ?62 dbc third harmonic v out = 2 v p-p, 5 mhz, r l, dm = 800 ?114 dbc v out = 2 v p-p, 20 mhz, r l, dm = 800 ?85 dbc v out = 2 v p-p, 70 mhz, r l, dm = 800 ?57 dbc imd 20 mhz ?77 dbc ip3 20 mhz 37 dbm voltage noise (rti) f = 100 khz to 40 mhz 5 nv/hz input current noise f = 100 khz to 40 mhz 2 pa/hz input characteristics offset voltage v os, dm = v out, dm /2; v din+ = v din? = v ocm = 0 v ?2.5 1 +2.5 mv t min to t max variation 4 v/c input bias current 3.5 7 a t min to t max variation ?0.01 a/c input resistance differential 6 m common mode 3 m input capacitance 1 pf input common-mode voltage ?4.7 to +3.4 v cmrr ?v out, dm /?v in, cm ; ?v in, cm = 1 v ?77 ?70 db output characteristics output voltage swing maximum ?v out ; single-ended output 7.75 v p-p output current 95 ma output balance error ?v out, cm /?v out, dm ; ?v out, dm = 1 v ?66 db 1 harmonic distortion performance is equal or slightly worse with higher values of r l, dm . see figure 17 and figure 18 for more information.
ad8138 rev. f | page 4 of 24 v ocm to out specifications at 25c, v s = 5 v, v ocm = 0, g = +1, r l, dm = 500 , unless otherwise noted. refer to figure 39 for test setup and label descriptions. all specifications refer to single-ended input and differential outputs, unless otherwise noted. table 2. parameter conditions min typ max unit dynamic performance ?3 db bandwidth 250 mhz slew rate 330 v/s input voltage noise (rti) f = 0.1 mhz to 100 mhz 17 nv/hz dc performance input voltage range 3.8 v input resistance 200 k input offset voltage v os, cm = v out, cm ; v din+ = v dinC = v ocm = 0 v C3.5 1 +3.5 mv input bias current 0.5 a v ocm cmrr ?v out, dm /?v ocm ; ?v ocm = 1 v ?75 db gain ?v out, cm /?v ocm ; ?v ocm = 1 v 0.9955 1 1.0045 v/v power supply operating range 1.4 5.5 v quiescent current 18 20 23 ma t min to t max variation 40 a/c power supply rejection ratio ?v out, dm /?v s ; ?v s = 1 v ?90 ?70 db operating temperature range ?40 +85 c
ad8138 rev. f | page 5 of 24 d in to out specifications at 25c, v s = 5 v, v ocm = 2.5 v, g = +1, r l, dm = 500 , unless otherwise noted. refer to figure 39 for test setup and label descriptions. all specifications refer to single-ended input and differential output, unless otherwise noted. table 3. parameter conditions min typ max unit dynamic performance ?3 db small signal bandwidth v out = 0.5 v p-p, c f = 0 pf 280 310 mhz v out = 0.5 v p-p, c f = 1 pf 225 mhz bandwidth for 0.1 db flatness v out = 0.5 v p-p, c f = 0 pf 29 mhz large signal bandwidth v out = 2 v p-p, c f = 0 pf 265 mhz slew rate v out = 2 v p-p, c f = 0 pf 950 v/s settling time 0.01%, v out = 2 v p-p, c f = 1 pf 16 ns overdrive recovery time v in = 2.5 v to 0 v step, g = +2 4 ns noise/harmonic performance 1 second harmonic v out = 2 v p-p, 5 mhz, r l, dm = 800 ?90 dbc v out = 2 v p-p, 20 mhz, r l, dm = 800 ?79 dbc v out = 2 v p-p, 70 mhz, r l, dm = 800 ?60 dbc third harmonic v out = 2 v p-p, 5 mhz, r l, dm = 800 ?100 dbc v out = 2 v p-p, 20 mhz, r l, dm = 800 ?82 dbc v out = 2 v p-p, 70 mhz, r l, dm = 800 ?53 dbc imd 20 mhz ?74 dbc ip3 20 mhz 35 dbm voltage noise (rti) f = 100 khz to 40 mhz 5 nv/hz input current noise f = 100 khz to 40 mhz 2 pa/hz input characteristics offset voltage v os, dm = v out, dm /2; v din+ = v dinC = v ocm = 0 v ?2.5 1 +2.5 mv t min to t max variation 4 v/c input bias current 3.5 7 a t min to t max variation ?0.01 a/c input resistance differential 6 m common mode 3 m input capacitance 1 pf input common-mode voltage ?0.3 to +3.2 v cmrr ?v out, dm /?v in, cm ; ?v in, cm = 1 v ?77 ?70 db output characteristics output voltage swing maximum ?v out ; single-ended output 2.9 v p-p output current 95 ma output balance error ?v out, cm /?v out, dm ; ?v out, dm = 1 v ?65 db 1 harmonic distortion performance is equal or slightly worse with higher values of r l, dm . see figure 17 and figure 18 for more information.
ad8138 rev. f | page 6 of 24 v ocm to out specifications at 25c, v s = 5 v, v ocm = 2.5 v, g = +1, r l, dm = 500 , unless otherwise noted. refer to figure 39 for test setup and label descriptions. all specifications refer to single-ended input and differential output, unless otherwise noted. table 4. parameter conditions min typ max unit dynamic performance ?3 db bandwidth 220 mhz slew rate 250 v/s input voltage noise (rti) f = 0.1 mhz to 100 mhz 17 nv/hz dc performance input voltage range 1.0 to 3.8 v input resistance 100 k input offset voltage v os, cm = v out, cm ; v din+ = v dinC = v ocm = 0 v ?5 1 +5 mv input bias current 0.5 a v ocm cmrr ?v out, dm /?v ocm ; ?v ocm = 2.5 v 1 v ?70 db gain ?v out, cm /?v ocm ; ?v ocm = 2.5 v 1 v 0.9968 1 1.0032 v/v power supply operating range 2.7 11 v quiescent current 15 20 21 ma t min to t max variation 40 a/c power supply rejection ratio ?v out, dm /?v s ; ?v s = 1 v ?90 ?70 db operating temperature range ?40 +85 c
ad8138 rev. f | page 7 of 24 absolute maximum ratings table 5. parameter ratings supply voltage 5.5 v v ocm v s internal power dissipation 550 mw operating temperature range ?40c to +85c storage temperature range ?65c to +150c lead temperature (soldering 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, ja is specified for the device soldered in a circuit board in still air. table 6. package type ja unit 8-lead soic/4-layer 121 c/w 8-lead msop/4-layer 145 c/w maximum power dissipation the maximum safe power dissipation in the ad8138 packages is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ad8138. exceeding a junction temperature of 150c for an extended period can result in changes in the silicon devices, potentially causing failure. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). the load current consists of the differential and common-mode currents flowing to the load, as well as currents flowing through the external feedback networks and internal common-mode feedback lo op. the internal resistor tap used in the common-mode feedback loop places a negligible differential load on the output. rms voltages and currents should be considered when dealing with ac signals. airflow reduces ja . in addition, more metal directly in contact with the package leads from metal traces through holes, ground, and power planes reduces the ja . figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8-lead soic (121c/w) and 8-lead msop ( ja = 145c/w) packages on a jedec standard 4-layer board. ja values are approximations. ambient temperature (c) maximum power dissipation (w) 1.75 1.50 1.00 1.25 0.50 0.25 0.75 0 soic msop 01073-049 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 110 120 figure 3. maximum power dissipation vs. temperature esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad8138 rev. f | page 8 of 24 pin configuration and fu nction descriptions ?in 1 v ocm 2 v+ 3 +out 4 +in 8 nc 7 v? 6 ?out 5 nc = no connect ad8138 01073-004 figure 4. pin configuration table 7. pin function descriptions pin no. mnemonic description 1 ?in negative input summing node. 2 v ocm voltage applied to this pin sets the common-mode output voltage with a ratio of 1:1. for example, 1 v dc on v ocm sets the dc bias level on +out and ?out to 1 v. 3 v+ positive supply voltage. 4 +out positive output. note that the voltage at ?d in is inverted at +out (see figure 42 ). 5 ?out negative output. note that the voltage at +d in is inverted at ?out (see figure 42 ). 6 v? negative supply voltage. 7 nc no connect. 8 +in positive input summing node.
ad8138 rev. f | page 9 of 24 typical performance characteristics unless otherwise noted, gain = 1, r g = r f = r l, dm = 499 v, t a = 25c; refer to figure 39 for test setup. frequency (mhz) gain (db) ?9 0 ?6 ?3 3 6 1 10 100 1000 v in =0.2vp-p c f =0pf v s =+5v v s =5v 01073-005 figure 5. small signal frequency response frequency (mhz) gain (db) ?9 0 ?6 ?3 3 6 1 10 100 1000 v s =5v v in =0.2vp-p c f =0pf c f =1pf 0 1073-006 figure 6. small signal frequency response gain (db) ?0.5 0.1 ?0.3 ?0.1 0.3 0.5 v s =5v v in =0.2vp-p c f =0pf c f =1pf frequency (mhz) 1 10 100 01073-007 figure 7. 0.1 db flatness vs. frequency frequency (mhz) gain (db) ?9 0 ?6 ?3 3 6 v in =2vp-p c f =0pf 1 10 100 1000 v s =+5v v s =5v 01073-008 figure 8. large signal frequency response frequency (mhz) gain (db) ?9 0 ?6 ?3 3 6 v in =2vp-p v s =5v c f =0pf c f =1pf 1 10 100 1000 01073-009 figure 9. large signal frequency response frequency (mhz) gain (db) ?10 10 0 20 30 v s =5v c f =0pf v out, dm =0.2vp-p r g = 499 ? g = 10, r f = 4.99k ? g=5,r f = 2.49k ? g=2,r f =1k ? g=1,r f =499 ? 1 10 100 1000 0 1073-010 figure 10. small signal frequency response for various gains
ad8138 rev. f | page 10 of 24 fundamental frequency (mhz) distortion (dbc) ? 50 ?120 ?90 ?100 ?110 ?70 ?80 ?60 v out, dm =2vp-p r l = 800 ? 0 10203040506070 hd2 (v s =+5v) hd2 (v s =5v) hd3 (v s =5v) hd3 (v s =+5v) 01073-011 figure 11. harmonic distortion vs. frequency fundamental frequency (mhz) distortion (dbc) ? 40 ?110 ?80 ?90 ?100 ?60 ?70 ?50 v out, dm =4vp-p r l = 800 ? 0 10203040506070 hd3 (v s =+5v) hd2 (v s =+5v) hd2 (v s =5v) hd3 (v s =5v) 01073-012 figure 12. harmonic distortion vs. frequency distortion (dbc) ?50 ?90 ?100 ?70 ?80 ?60 ?40 ? 30 hd2 (v s =+5v) hd3 (v s =+5v) hd3 (v s =5v) v out, dm =2vp-p r l =800 ? f o = 20mhz v ocm dc output (v) ?4?3?2?101234 hd2 (v s =5v) 0 1073-013 figure 13. harmonic distortion vs. v ocm 0 6 ?120 ?90 ?100 ?110 ?70 ?80 ? 60 5 4 3 2 1 differential output voltage (v p-p) distortion (dbc) v s =5v r l = 800 ? hd3 (f = 20mhz) hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) 01073-014 figure 14. harmonic distortion vs. differential output voltage differential output voltage (v p-p) distortion (dbc) ?120 ?90 ?100 ?110 ?70 ?80 ? 60 v s =5v r l = 800 ? hd3 (f = 5mhz) hd2 (f = 5mhz) hd3 (f = 20mhz) hd2 (f = 20mhz) 0123 01073-015 4 figure 15. harmonic distortion vs. differential output voltage distortion (dbc) ?90 ?100 ?110 ?70 ?80 ? 60 0.25 1.75 1.50 1.25 1.00 0.75 0.50 differential output voltage (v p-p) v s =3v r l = 800 ? hd3 (f = 5mhz) hd2 (f = 5mhz) hd3 (f = 20mhz) hd2 (f = 20mhz) 01073-016 figure 16. harmonic distortion vs. differential output voltage
ad8138 rev. f | page 11 of 24 distortion (dbc) ?90 ?100 ?110 ?70 ?80 ? 60 v s =5v v out, dm =2vp-p hd2 (f = 20mhz) hd3 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) r load ( ? ) 200 600 1000 1400 1800 01073-017 figure 17. harmonic distortion vs. r load ?90 ?100 ?110 ?70 ?80 ? 60 ?120 200 600 1000 1400 1800 r load ( ? ) distortion (dbc) hd3 (f = 5mhz) hd2 (f = 5mhz) hd3 (f = 20mhz) hd2 (f = 20mhz) v s =5v v out, dm =2vp-p 01073-018 figure 18. harmonic distortion vs. r load frequency (mhz) ?50 ?90 ?110 ?70 ?30 ?10 10 49.5 49.7 49.9 50.1 50.3 50.5 f c =50mhz v s =5v p out (dbm) 0 1073-019 figure 19. intermodulation distortion frequency (mhz) intercept (dbm) 30 25 35 40 45 r l =800 ? v s =+5v v s =5v 02 04 06 0 01073-020 8 0 figure 20. third-order intercept vs. frequency v s =5v v out, dm v out+ v out? v +din 5ns 1v 01073-021 figure 21. large signal transient response v out, dm =0.2vp-p v s =5v c f =0pf c f =1pf 5ns 40mv 01073-022 figure 22. small signal transient response
ad8138 rev. f | page 12 of 24 v out, dm =2vp-p c f =0pf v s =5v v s =+5v 5ns 400mv 0 1073-023 figure 23. large signal transient response v out, dm =2vp-p v s =5v c f =0pf c f =1pf 5ns 400mv 01073-024 figure 24. large signal transient response 4ns 1v v +din v out, dm 200v v s =5v c f =1pf 01073-025 figure 25. settling time 30ns 4v v out, dm v +din v s =5v f=20mhz v +din =8vp-p g=3(r f = 1500) 01073-026 figure 26. output overdrive v s =5v c f =0pf c l = 20pf c l =5pf 2.5ns 400mv c l =10pf 01073-028 figure 27. large signal transient response for various cap loads (see figure 40 ) frequency (mhz) cmrr (db) ? 20 ?30 ?40 ?50 ?60 ?70 ?80 v s =5v v out, dm / v in, cm 11 01 0 0 1 k 0 1073-029 figure 28. cmrr vs. frequency
ad8138 rev. f | page 13 of 24 frequency (mhz) balance error (db) ? 20 ?30 ?40 ?50 ?60 ?70 v in =2vp-p v s =5v v s =+5v 1 10 100 1k 01073-031 figure 29. output balanc e error vs. frequency (see figure 41 ) frequency (mhz) psrr (db) ?20 ?30 ?40 ?50 ?60 ?70 ? 10 ?80 ?90 +psrr (v s = +5v, 0v and 5v) ?psrr (v s =5v) v out, dm / v s 1 10 100 1k 01073-032 figure 30. psrr vs. frequency frequency (mhz) impedance ( ? ) 100 0.1 1 10 1 10 100 v s =5v v s =+5v single-ended output 01073-033 figure 31. output im pedance vs. frequency differential output offset (mv) ?5.0 ?2.5 0 2.5 5.0 temperature (c) ?40 ?20 0 20 40 60 80 100 v s =+3v v s =+5v v s =5v 0 1073-034 figure 32. output referred different ial offset voltag e vs. temperature 2 4 5 1 3 bias current (a) temperature (c) ?40 ?20 0 20 40 60 80 100 v s =5v,+5v v s =+3v 01073-035 figure 33. input bias current vs. temperature 10 5 15 20 25 30 temperature (c) supply current (ma) v s =5v v s =+5v v s =+3v ?40 ?20 0 20 40 60 80 100 0 1073-036 figure 34. supply current vs. temperature
ad8138 rev. f | page 14 of 24 frequency (mhz) ?9 0 ?6 ?3 3 6 v s =+5v v s =5v gain (db) 1 10 100 1k 01073-037 figure 35. v ocm frequency response 5ns 400mv v out, cm v s =5v v ocm =?1vto+1v 01073-038 figure 36. v ocm transient response frequency (hz) input current noise (pa/ hz) 100 1 10 1.1pa/ hz 100 10 1k 10k 100k 1m 01073-039 figure 37. current noise (rti) frequency (hz) input voltage noise (nv/ hz) 100 1 10 1000 5.7nv/ hz 10 100 1k 10k 100k 1m 01073-040 figure 38. voltage noise (rti)
ad8138 rev. f | page 15 of 24 test circuits ad8138 24.9 ? 49.9 ? r f = 499 ? r f = 499 ? r l, dm =499 ? r g = 499 ? r g = 499 ? 0 1073-003 figure 39. basic test circuit c l 499 ? 49.9 ? 24.9 ? 453 ? ad8138 24.9 ? 24.9 ? 499 ? 499 ? 499 ? 01073-027 figure 40. test circuit for cap load drive 499 ? 49.9 ? 24.9 ? ad8138 249 ? 249 ? 499 ? 499 ? 499 ? 01073-030 figure 41. test circuit for output balance
ad8138 rev. f | page 16 of 24 operational description definition of terms ad8138 +in ?in +out ?out c f c f r f r f +d in ?d in v ocm r g r g v out, dm r l, dm 01073-041 figure 42. circuit definitions differential voltage refers to the difference between two node voltages. for example, the output differential voltage (or equivalently output differential-mode voltage) is defined as v out, dm = ( v +out ? v ?out ) where v +out and v ?out refer to the voltages at the +out and ?out terminals with respect to a common reference. common-mode voltage refers to the average of two node voltages. the output common-mode voltage is defined as v out, cm = ( v +out + v ?out )/2 balance is a measure of how well differential signals are matched in amplitude and exactly 180 apart in phase. balance is most easily determined by placing a well-matched resistor divider between the differential voltage nodes and comparing the magnitude of the signal at the dividers midpoint with the magnitude of the differential signal (see figure 41 ). by this definition, output balance is the magnitude of the output common-mode voltage divided by the magnitude of the output differential mode voltage: dmout cmout v v error balance output , , =
ad8138 rev. f | page 17 of 24 theory of operation the ad8138 differs from conventional op amps in that it has two outputs whose voltages move in opposite directions. like an op amp, it relies on high open-loop gain and negative feedback to force these outputs to the desired voltages. the ad8138 behaves much like a standard voltage feedback op amp and makes it easy to perform single-ended-to-differential conversion, common-mode level-shifting, and amplification of differential signals. also like an op amp, the ad8138 has high input impedance and low output impedance. previous differential drivers, both discrete and integrated designs, have been based on using two independent amplifiers and two independent feedback loops, one to control each of the outputs. when these circuits are driven from a single-ended source, the resulting outputs are typically not well balanced. achieving a balanced output has typically required exceptional matching of the amplifiers and feedback networks. dc common-mode level-shifting has also been difficult with previous differential drivers. level-shifting has required the use of a third amplifier and feedback loop to control the output common-mode level. sometimes the third amplifier has also been used to attempt to correct an inherently unbalanced circuit. excellent performance over a wide frequency range has proven difficult with this approach. the ad8138 uses two feedback loops to separately control the differential and common-mode output voltages. the differential feedback, set with external resistors, controls only the differential output voltage. the common-mode feedback controls only the common-mode output voltage. this architecture makes it easy to arbitrarily set the output common-mode level. it is forced, by internal common-mode feedback, to be equal to the voltage applied to the v ocm input, without affecting the differential output voltage. the ad8138 architecture results in outputs that are very highly balanced over a wide frequency range without requiring tightly matched external components. the common-mode feedback loop forces the signal component of the output common-mode voltage to be zeroed. the result is nearly perfectly balanced differential outputs of identical amplitude and exactly 180 apart in phase. analyzing an application circuit the ad8138 uses high open-loop gain and negative feedback to force its differential and common-mode output voltages in such a way as to minimize the differential and common-mode error voltages. the differential error voltage is defined as the voltage between the differential inputs labeled +in and ?in in figure 42 . for most purposes, this voltage can be assumed to be zero. similarly, the difference between the actual output common- mode voltage and the voltage applied to v ocm can also be assumed to be zero. starting from these two assumptions, any application circuit can be analyzed. setting the closed-loop gain neglecting the capacitors c f , the differential-mode gain of the circuit in figure 42 can be determined to be described by s g s f dmout dmout r r v v = , , this assumes the input resistors, r g s , and feedback resistors, r f s , on each side are equal. estimating the output noise voltage similar to the case of a conventional op amp, the differential output errors (noise and offset voltages) can be estimated by multiplying the input referred terms, at +in and ?in, by the circuit noise gain. the noise gain is defined as ? ? ? ? ? ? ? ? += g f n r r g 1 to compute the total output referred noise for the circuit of figure 42 , consideration must also be given to the contribution of the resistors r f and r g . refer to table 8 for the estimated output noise voltage densities at various closed-loop gains. table 8. gain r g () r f () bandwidth ? 3 db output noise ad8138 only output noise ad8138 + r g , r f 1 499 499 320 mhz 10 nv/hz 11.6 nv/hz 2 499 1.0 k 180 mhz 15 nv/hz 18.2 nv/hz 5 499 2.49 k 70 mhz 30 nv/hz 37.9 nv/hz 10 499 4.99 k 30 mhz 55 nv/hz 70.8 nv/hz
ad8138 rev. f | page 18 of 24 when using the ad8138 in gain configurations where g f r r of one feedback network is unequal to g f r r of the other network, there is a differential output noise due to input-referred voltage in the v ocm circuitry. the output noise is defined in terms of the following feedback terms (refer to figure 42 ): g f g rr r + = 1 for ?out to +in loop, and g f g rr r + = 2 for +out to ?in loop. with these defined, ? ? ? ? ? ? ? ? + ? = 21 21 , , 2 ocm vnin dmnout v v where v nout, dm is the output differential noise, and is the input-referred voltage noise in v ocm . com vnin v , the impact of mismatch es in the feedback networks as previously mentioned, even if the external feedback networks (r f /r g ) are mismatched, the internal common-mode feedback loop still forces the outputs to remain balanced. the amplitudes of the signals at each output remains equal and 180 out of phase. the input-to-output differential-mode gain varies proportionately to the feedback mismatch, but the output balance is unaffected. ratio matching errors in the external resistors result in a degradation of the circuits ability to reject input common- mode signals, much the same as for a four-resistor difference amplifier made from a conventional op amp. in addition, if the dc levels of the input and output common- mode voltages are different, matching errors result in a small differential-mode output offset voltage. for the g = 1 case, with a ground referenced input signal and the output common-mode level set for 2.5 v, an output offset of as much as 25 mv (1% of the difference in common-mode levels) can result if 1% tolerance resistors are used. resistors of 1% tolerance result in a worst- case input cmrr of about 40 db, worst-case differential mode output offset of 25 mv due to 2.5 v level-shift, and no significant degradation in output balance error. calculating an application circuits input impedance the effective input impedance of a circuit such as the one in figure 42 , at +din and Cdin, depends on whether the amplifier is being driven by a single-ended or differential signal source. for balanced differential input signals, the input impedance ( r in, dm ) between the inputs (+d in and ?d in ) is simply r in, dm =2 r g in the case of a single-ended input signal (for example if ?d in is grounded and the input signal is applied to +d in ), the input impedance becomes () ? ? ? ? ? ? ? ? ? ? ? ? + ? = f g f g dmin rr r r r 2 1 , the circuits input impedance is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor r g . input common-mode voltage range in single-supply applications the ad8138 is optimized for level-shifting, ground-referenced input signals. for a single-ended input, this would imply, for example, that the voltage at ?d in in figure 42 would be 0 v when the amplifiers negative power supply voltage (at v?) is also set to 0 v. setting the output common-mode voltage the ad8138s v ocm pin is internally biased at a voltage approximately equal to the midsupply point (average value of the voltages on v+ and v?). relying on this internal bias results in an output common-mode voltage that is within about 100 mv of the expected value. in cases where more accurate control of the output common- mode level is required, it is recommended that an external source, or resistor divider (made up of 10 k resistors), be used. the output common-mode offset listed in the specifications section assumes the v ocm input is driven by a low impedance voltage source. driving a capacitive load a purely capacitive load can react with the pin and bondwire inductance of the ad8138, resulting in high frequency ringing in the pulse response. one way to minimize this effect is to place a small capacitor across each of the feedback resistors. the added capacitance should be small to avoid destabilizing the amplifier. an alternative technique is to place a small resistor in series with the amplifiers outputs, as shown in figure 40 .
ad8138 rev. f | page 19 of 24 layout, grounding, and bypassing as a high speed part, the ad8138 is sensitive to the pcb environment in which it has to operate. realizing its superior specifications requires attention to various details of good high speed pcb design. the first requirement is for a good solid ground plane that covers as much of the board area around the ad8138 as possible. the only exception to this is that the two input pins (pin 1 and pin 8) should be kept a few millimeters from the ground plane, and ground should be removed from inner layers and the opposite side of the board under the input pins. this minimizes the stray capacitance on these nodes and helps preserve the gain flatness vs. frequency. the power supply pins should be bypassed as close as possible to the device to the nearby ground plane. good high frequency ceramic chip capacitors should be used. this bypassing should be done with a capacitance value of 0.01 f to 0.1 f for each supply. further away, low frequency bypassing should be provided with 10 f tantalum capacitors from each supply to ground. the signal routing should be short and direct to avoid parasitic effects. wherever there are complementary signals, a symmetrical layout should be provided to the extent possible to maximize the balance performance. when running differential signals over a long distance, the traces on the pcb should be close together or any differential wiring should be twisted together to minimize the area of the loop that is formed. this reduces the radiated energy and makes the circuit less susceptible to interference.
ad8138 rev. f | page 20 of 24 balanced transformer driver transformers are among the oldest devices used to perform a single-ended-to-differential conversion (and vice versa). trans- formers can also perform the additional functions of galvanic isolation, step-up or step-down of voltages, and impedance transformation. for these reasons, transformers always find uses in certain applications. however, when driving the transformer in a single-ended manner, there is an imbalance at the output due to the parasitics inherent in the transformer. the primary (or driven) side of the transformer has one side at dc potential (usually ground), while the other side is driven. this can cause problems in systems that require good balance of the transformers differential output signals. if the interwinding capacitance (c stray ) is assumed to be uniformly distributed, a signal from the driving source couples to the secondary output terminal that is closest to the primarys driven side. on the other hand, no signal is coupled to the opposite terminal of the secondary because its nearest primary terminal is not driven (see figure 43 ). the exact amount of this imbalance depends on the particular parasitics of the trans- former, but is mostly a problem at higher frequencies. the balance of a differential circuit can be measured by connecting an equal-valued resistive voltage divider across the differential outputs and then measuring the center point of the circuit with respect to ground. since the two differential outputs are supposed to be of equal amplitude, but 180 opposite phase, there should be no signal present for perfectly balanced outputs. the circuit in figure 43 shows a mini-circuits? t1-6t transformer connected with its primary driven single-endedly and the secondary connected with a precision voltage divider across its terminals. the voltage divider is made up of two 500 , 0.005% precision resistors. the voltage v unbal , which is also equal to the ac common-mode voltage, is a measure of how closely the outputs are balanced. figure 45 compares the transformer being driven single- endedly by a signal generator and being driven differentially using an ad8138. the top signal trace of figure 45 shows the balance of the single-ended configuration, while the bottom shows the differentially driven balance response. the 100 mhz balance is 35 db better when using the ad8138. the well-balanced outputs of the ad8138 provide a drive signal to each of the transformers primary inputs that are of equal amplitude and 180 out of phase. therefore, depending on how the polarity of the secondary is connected, the signals that conduct across the interwinding capacitance either both assist the transformers secondary signal equally, or both buck the secondary signals. in either case, the parasitic effect is symmetrical and provides a well-balanced transformer output (see figure 45 ). primary c stray c stray 52.3 ? secondary v diff 500 ? 0.005% 500 ? 0.005% v unbal sign a liscoupled on this side via c stray no signal is coupled on this side 01073-042 figure 43. transformer si ngle-ended-to-differential converter is inherently imbalanced v diff v unbal ad8138 +in ?in out+ out? 499 ? 499? 499? 499 ? 49.9 ? 49.9 ? 500 ? 0.005% 500 ? 0.005% c stray c stray 01073-043 figure 44. ad8138 forms a balanced transformer driver frequency (mhz) 0 output balance error (db) ?20 ?40 ?60 ?80 ?100 0.3 1 10 100 500 v unbal , differential drive v unbal , for transformer with single-ended drive 0 1073-044 figure 45. output balance error for circuits of figure 43 and figure 44
ad8138 rev. f | page 21 of 24 high performance adc driving the circuit in figure 46 shows a simplified front-end connection for an ad8138 driving an ad9224 , a 12-bit, 40 msps adc. the adc works best when driven differentially, which minimizes its distortion. the ad8138 eliminates the need for a transformer to drive the adc and performs single- ended-to-differential conversion, common-mode level-shifting, and buffering of the driving signal. the positive and negative outputs of the ad8138 are connected to the respective differential inputs of the ad9224 via a pair of 49.9 resistors to minimize the effects of the switched-capacitor front end of the ad9224 . for best distortion performance, it runs from supplies of 5 v. the ad8138 is configured with unity gain for a single-ended, input-to-differential output. the additional 23 , 523 total, at the input to ?in is to balance the parallel impedance of the 50 source and its 50 termination that drives the noninverting input. the signal generator has a ground-referenced, bipolar output, that is, it drives symmetrically above and below ground. connecting v ocm to the cml pin of the ad9224 sets the output common-mode of the ad8138 at 2.5 v, which is the midsupply level for the ad9224 . this voltage is bypassed by a 0.1 f capacitor. the full-scale analog input range of the ad9224 is set to 4 v p-p, by shorting the sense terminal to avss. this has been determined to be the scaling to provide minimum harmonic distortion. for the ad8138 to swing at 4 v p-p, each output swings 2 v p-p while providing signals that are 180 out of phase. with a common-mode voltage at the output of 2.5 v, each ad8138 output swings between 1.5 v and 3.5 v. a ground-referenced 4 v p-p, 5 mhz signal at d in + was used to test the circuit in figure 46 . when the combined-device circuit was run with a sampling rate of 20 msps, the spurious-free dynamic range (sfdr) was measured at ?85 dbc. 49.9 ? 0.1pf 523 ? 499 ? 49.9 ? 499 ? 499 ? vinb +5v drvdd avdd vina +5 v ad9224 v ocm ad8138 ?5v sense + digital outputs 0.1pf 0.1pf drvss cml avss 49.9 ? 50 ? source 8 2 1 6 3 5 4 24 23 15 26 16 25 28 17 22 27 01073-045 figure 46. ad8138 driving an ad9224, a 12-bit, 40 msps adc
ad8138 rev. f | page 22 of 24 3 v operation the circuit in figure 47 shows a simplified front-end connection for an ad8138 driving an ad9203 , a 10-bit, 40 msps adc that is specified to work on a single 3 v supply. the adc works best when driven differentially to make the best use of the signal swing available within the 3 v supply. the appropriate outputs of the ad8138 are connected to the appropriate differential inputs of the ad9203 via a low-pass filter. the ad8138 is configured for unity gain for a single-ended input to differential output. the additional 23 at the input to ?in is to balance the impedance of the 50 source and its 50 termination that drives the noninverting input. the signal generator has ground-referenced, bipolar output, that is, it can drive symmetrically above and below ground. even though the ad8138 has ground as its negative supply, it can still function as a level-shifter with such an input signal. the output common mode is raised up to midsupply by the voltage divider that biases v ocm . in this way, the ad8138 provides dc coupling and level-shifting of a bipolar signal, without inverting the input signal. the low-pass filter between the ad8138 and the ad9203 provides filtering that helps to improve the signal-to-noise ratio (snr). lower noise can be realized by lowering the pole frequency, but the bandwidth of the circuit is lowered. 49.9 ? 0.1f 10k ? 523 ? 499 ? 10k ? 20pf 49.9 ? 20pf 499 ? 499 ? 0.1f 3v drvdd avdd ainn ainp 0.1f 0.1f 3 v 49.9 ? ad8138 + ad9203 8 2 1 3 5 4 6 28 2 27 25 26 1 avss drvss digital outputs 01073-046 figure 47. ad8138 driving an ad9203 , a 10-bit, 40 msps a/d converter the circuit was tested with a ?0.5 dbfs signal at various frequencies. figure 48 shows a plot of the total harmonic distortion (thd) vs. frequency at signal amplitudes of 1 v and 2 v differential drive levels. frequency (mhz) ? 40 thd (dbc) ?45 ?50 ?55 ?60 ?65 ?70 ?75 ?80 ad8138?2v ad8138?1v 0 5 10 15 20 25 01073-047 figure 48. ad9203 thd @ ?0.5 dbfs ad8138 figure 49 shows the signal-to-noise-plus distortion (sinad) under the same conditions as above. for the smaller signal swing, the ad8138 performance is quite good, but its performance degrades when trying to swing too close to the supply rails. frequency (mhz) 65 sinad (dbc) 63 61 59 57 55 53 51 45 49 47 ad8138?1v ad8138?2v 0 5 10 15 20 25 01073-048 figure 49. ad9203 sinad @ ?0.5 dbfs ad8138
ad8138 rev. f | page 23 of 24 outline dimensions 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa figure 50. 8-lead standard small outline package [soic] (r-8) dimensions shown in millimeters and (inches) compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 51. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters ordering guide model temperature range package descri ption package option branding ad8138ar ?40c to +85c 8-lead soic r-8 ad8138ar-reel ?40c to +85c 8-lead soic, 13" tape and reel r-8 ad8138ar-reel7 ?40c to +85c 8-lead soic, 7" tape and reel r-8 ad8138arz 1 ?40c to +85c 8-lead soic r-8 ad8138arz-rl 1 ?40c to +85c 8-lead soic, 13" tape and reel r-8 AD8138ARZ-R7 1 ?40c to +85c 8-lead soic, 7" tape and reel r-8 ad8138arm ?40c to +85c 8-lead msop rm-8 hba ad8138arm-reel ?40c to +85c 8-lead msop, 13" tape and reel rm-8 hba ad8138arm-reel7 ?40c to +85c 8-lead msop, 7" tape and reel rm-8 hba ad8138armz 1 ?40c to +85c 8-lead msop rm-8 hba# ad8138armz-reel 1 ?40c to +85c 8-lead msop, 13" tape and reel rm-8 hba# ad8138armz-reel7 1 ?40c to +85c 8-lead msop, 7" tape and reel rm-8 hba# 1 z = pb-free part, # denotes lead-free product may be top or bottom marked.
ad8138 rev. f | page 24 of 24 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c01073-0-1/06(f)

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